1. Field of the Invention
The present invention relates generally to a system and method for quality control of integrated circuits manufactured by a semiconductor manufacturing process and, more particularly, to a system and method for analyzing defects in integrated circuits manufactured using a semiconductor fabrication process.
2. Description of the Prior Art
The semiconductor manufacturing industry is continually evolving its fabrication processes and developing new processes to produce smaller and smaller geometries of the semiconductor devices being manufactured, because smaller devices typically generate less heat and operate at higher speeds than larger devices. Currently, a single integrated circuit chip may contain over one billion patterns. The occurrence of defects may cause lower yield in the final semiconductor product, where yield may be defined as the number of functional devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving yield is a critical problem in the semiconductor manufacturing industry and has a direct economic impact on it. In particular, a higher yield translates into more devices that may be sold by the manufacturer, and greater profits.
Typically, semiconductor manufacturers collect data about various defects and analyze the data and, based on data analysis, adjust the integrated circuit design or process steps or tool specifications in an attempt to improve the yield of the process. This has created a need for a new generation of tools and techniques for defect analysis for semiconductor yield management.
U.S. Pat. No. 6,470,229 B1 assigned to the same assignee as the present application discloses a yield management system and technique to generate a yield model. The system can also accept user input to modify the generated model.
Additionally, a Genesis™ Bitmap Analysis product module is commercially available from the assignee of U.S. Pat. No. 6,470,229 B1 to extend the capabilities of the yield management system to direct bitmap-level analysis. The Bitmap Analysis product module suite allows a user to graph and analyze bitmap data. Bit failures are revealed to the user visually with interactive bitmaps. Analysis is performed on classified bitmap pattern information imported into a data sheet. Patterns may consist of single-bit fails, dual bits, rows, columns, etc. A general instance of a fail is described internally preferably using a list of one or more bounding rectangles to specify the set of bits that failed. Each bounding rectangle is specified by the bit coordinates of the lower-left and upper-right corners of the rectangle.
Information on each of a die's bit failures can be viewed by toggling an “N of (total number of bit fails)” list in a Bit-Fail Browser. The following information may be displayed for each bit failure:                Array—the array where the bit failure occurred.        Block—the block where the bit failure occurred.        Pattern—the bit-fail pattern associated with the bit failure. If the bit failure is not associated with a defined bit-fail pattern, this field will be grayed out.        Bit Count—this field specifies the total number of bits that failed in the defined rectangle associated with the bit-fail pattern. The rectangle is defined by Array, Block, and physical coordinates (X0, Y0) and (X1, Y1).        Sub-Pattern—the index of the bounding rectangle(s) in the bit-fail pattern. Each sub-pattern has a range.        Range—the X0, X1, Y0, and Y1 coordinates describe the lower-left corner (X0, Y0) and the upper-right corner (X1, Y1) of the bounding rectangle associated with the current sub-pattern. These coordinates are in units of bits from the lower-left corner of the array/block.        Match—if this option is checked by a user, the bit failure has been matched to a known defect.        Reticle Repeater—if this option is checked by the user, the bit failure is repeating on the same reticle.        
Random failed bits are common in memory devices and in embedded memory in system-on-chip integrated circuits. Failed bits are typically classified into a pattern name using a rigid predefined group of bits. Some examples of common predefined patterns are “single bit,” “pair bits,” “group of bits,” etc. These predefined patterns allow a bitmap classifier to identify and match a group of bits to the patterns. There are two major problems that arise with this technique.
First, random individual bits and groups of bits that fail near each other are typically caused by the same process event and should be classified to the same pattern, rather than many individual patterns. Second, these seemingly random individual bits and groups of bits are sometimes systematic in nature, meaning that they almost always failed certain ways. If the patterns are not defined ahead of time, these systematic cluster bits will not be identified in a timely manner. New memory design and new memory testing techniques may produce these systematic patterns, unknowingly to the user.
Thus, it would be desirable to provide a defect analysis system and method which overcome the above limitations and disadvantages of conventional systems and facilitate bitmap analysis leading to more effective quality control. It is to this end that the present invention is directed. The various embodiments of the bit clustering and aggregation system and method in accordance with the present invention address the two aforementioned problems and provide many advantages over conventional defect bitmap analysis systems and techniques.